Field of the Invention
The invention relates to a method for pattern etching a gate stack layer on a substrate.
Description of Related Art
As the size of semiconductor devices is reduced, process development and integration issues are key challenges for new gate materials including high-permittivity (or high dielectric constant) dielectric materials (also referred to herein as high-k materials).
Dielectric materials featuring a dielectric constant greater than that of SiO2 (k˜3.9) are commonly referred to as high-k materials. In addition, high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrate (e.g., SiO2, SiNxOy). High-k materials may incorporate metallic silicates or oxides (e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiO, HfO2 (k˜25)).
For front-end-of-line (FEOL) operations, these high-k materials are contemplated for integration with polycrystalline silicon (polysilicon) gate structures and, in the longer term, they are contemplated for use with metal gates. However, the integration of high-k materials with gate structures has posed substantive challenges during the patterning of the gate structure. In particular, conventional etching processes suffer from poor profile control and substrate recess formation during pattern transfer.